This application claims priority to Korean Patent Application No. 2001-6985, filed Feb. 13, 2001, the disclosure of which is hereby incorporated herein by reference.
The invention relates to methods of forming integrated circuits, and more particularly, to methods of forming integrated circuits having spin-on-glass layers.
As techniques of manufacturing semiconductor devices develop, the integration density of semiconductor devices may increase and, associated design rules for forming the semiconductor device may decrease. Accordingly, the distance between adjacent conductive layers on the same layer can decrease and thus, the aspect ratio of the height of a gap between adjacent conductive layers to the width of the gap between adjacent conductive layers increases. Therefore, a method of filling the gap between conductive layers having high aspect ratios may be useful.
It is know to use a Boron Phosphorus Silicate Glass (BPSG) layer and a high density plasma (HDP) oxide layer as an interlayer dielectric layer to fill the gaps discussed above. However, in the case of using the BPSG layer, a temperature of 800xc2x0 C. or greater may be needed. In the case of using the HDP oxide layer, if the aspect ratio is greater than 2.5, the gap filling capability of the HDP oxide layer may be considerably diminished.
It is known to use a Spin-On-Glass (SOG) layer as an interlayer dielectric layer instead of the BPSG layer and the HDP oxide layer discussed above. The SOG layer exists in a liquid state at room temperature and thus, can exhibit superior gap filling capability if it is densified through a curing process.
FIGS. 1 and 2 are cross-sectional diagrams illustrating a method of patterning a conventional SOG layer. Referring to FIG. 1, a semiconductor substrate 10 on which a predetermined pattern has been formed is coated with a SOG layer 12. Next, the SOG layer 12 is cured to be densified. However, the lower part of the SOG layer 12 is susceptible to insufficient densification by curing. The lower part of the SOG layer 12, which is not sufficiently densified, may exhibit inferior gap filling characteristics in the subsequent cleaning process, which will be described in detail below.
A hard mask material is deposited on the SOG layer 12 and then, a hard mask pattern 14 is formed by using photolithography and etching. After that, the SOG layer 12 is etched using the hard mask pattern 14 as an etching mask so that a predetermined portion of the semiconductor substrate 10 can be exposed. Referring to FIG. 2, the exposed portions of the semiconductor substrate 10 are cleaned to reduce a contact resistance between the semiconductor substrate 10 and a pad or a contact plug. In the cleaning process, standard cleaning 1 cleaner (mixed liquid of ammonium hydroxide, peroxide and deionized water) can be used. The lower part of the SOG layer 12a, which was not sufficiently cured, can be etched more rapidly than the upper part of the SOG layer 12b which was sufficiently cured.
As described above, the SOG can exhibit the problem in that its lower part is not sufficiently cured. Due to this phenomenon, the profile of a SOG layer pattern may become deteriorated in a subsequent cleaning process as shown by the erratic profile of the layer 12a. In some extreme situations, the lower part of the SOG layer 12a may be completely removed, thereby possibly completely destroying the SOG layer pattern. In addition, if the SOG layer is not satisfactorily cured, it may exhibit hydroscopic and outgasing characteristics. These characteristics can bring about contact failure introduced by a deteriorated contact profile and oxidation of metal interconnections caused by absorption of moisture or outgasing.
Embodiments according to the invention can provide methods of forming a Spin-On-Glass (SOG) layer. Pursuant to these embodiments, an SOG layer is formed on an integrated circuit substrate. A first curing process is performed on the SOG layer. Less than all of the SOG layer is removed from the integrated circuit substrate through a mask pattern on the SOG layer to provide a remaining portion of the SOG layer on the integrated circuit substrate. A second curing process is performed on the SOG layer. The remaining portion of the SOG layer is removed to expose the integrated circuit substrate.
In some embodiments according to the invention, the SOG layer is etched through the mask pattern to form a recess in the SOG layer, wherein the recess has a bottom formed of the SOG layer that is spaced-apart from the integrated circuit substrate by a thickness of the bottom.
In some embodiments according to the invention, etching the bottom is followed by cleaning the integrated circuit substrate and forming a conductive layer in the recess on the integrated circuit substrate.
In some embodiments according to the invention, performing the first curing process includes performing the first curing process at a temperature in a range between about 600xc2x0 C. and about 800xc2x0 C. for a time in a range between about 20 minutes and about 2 hours.
In some embodiments according to the invention, performing the second curing process includes performing the second curing process at a temperature in a range between about 400xc2x0 C. and about 800xc2x0 C. for a time in a range between about 10 minutes and about 1 hour.
In some embodiments according to the invention, the first and second curing processes are performed using H2O, O2, N2, H2, NO2 or a mixture of these gases as an atmospheric gas.
In some embodiments according to the invention, the remaining portion has a thickness that is adequate to prevent oxidation of the integrated circuit substrate during the second curing process. In some embodiments according to the invention, the thickness is in a range between about 300 xc3x85ngstroms and about 500 xc3x85ngstroms.
In some embodiments according to the invention, the etching is performed using a Cxe2x80x94F based gas, CO gas, O2 gas and an inert gas as etching gas, reaction gas and atmospheric gas, respectively. In some embodiments according to the invention, the etching is performed at an RF power in a range between about 1000 Watts and about 2000 Watts at a pressure in a range between about 10 mTorr and about 100 mTorr and a temperature in a range between about 0xc2x0 C. and about 60xc2x0 C. for a time in a range between about 20 seconds and about 50 seconds.
In some embodiments according to the invention, the etching is performed using at an RF power in a range between about 1000 Watts and about 2000 Watts at a pressure in a range between about 10 mTorr and about 100 mTorr and a temperature in a range between about 0xc2x0 C. and about 60xc2x0 C. for a time in a range between about 5 second and about 30 seconds.
In some embodiments according to the invention, the mask pattern is formed of a polysilicon layer, an aluminum oxide layer (Al2O3), an aluminum nitride layer (AlN) or a silicon nitride layer (Si3N4).